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40-channel, 3 v/5 v, single-supply, serial, 14-bit voltage output dac ad5384 rev. a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures guar ant e e d m o not o ni c i n l e r ro r: 4 l s b m a x o n - c hip 1.25 v/ 2.5 v , 10 p p m/ c ref e renc e t e mper a t ure r a nge: C40c t o + 85c r a il-t o - r a i l out p ut amplifier p o w e r- down p a ck age t y pe: 100-le ad cspbga (1 0 mm 1 0 mm) u s er int e r f ac es : s e rial (spi-?/qspi-?/micr owire-?/dsp - c o mpa t ible , f e a t uring da ta r eadback) i 2 c-?c ompa tibl e integr a t e d fu nc ti o n s channel monitor simultaneo us o u tput update via ld a c clear f u nc tion t o user-pr o gr ammable c o de a m plifier boost mode t o optimiz e sle w r a t e u s er-pr o gr ammable off s et a n d gain adjust t o ggle mode enables squar e wa v e gener a ti on t h ermal monitor applic a t io ns v a riable optic a l a t t e nuat ors ( v o a ) le v e l setting ( a te) o p ti c a l micr o - elec tr o - mecha n ic al sy st ems ( m ems) c o n t r o l sy st em s instrumen t a t ion func ti on a l bl ock di a g r a m r r vout0 dac 0 dac reg 0 input reg 0 14 14 14 14 14 14 m reg 0 c reg 0 1.25v/2.5v reference power-on reset 39-to-1 mux r r vout1 vout2 vout3 vout4 vout5 dac 1 dac reg 1 input reg 1 14 14 14 14 14 14 m reg 1 c reg 1 r r vout6 dac 6 dac reg 6 input reg 6 14 14 14 14 14 14 m reg 6 c reg 6 r r vout7 vout8 dac 7 dac reg 7 input reg 7 14 14 14 14 14 14 m reg 7 c reg 7 5 04652-0-001 state machine + control logic interface control logic vout0??vout38 reset busy clr pd din/sda spi/i 2 c sclk/scl sync/ad 0 dcen/ad 1 sdo vout39/mon_out ldac vout38 dvdd (3) dgnd (4) avdd ( 5) agnd (5) dac gnd (5) refgnd refout/refin signal gnd ( 5) ad5384 fi g u r e 1 .
ad5384 rev. a | page 2 of 36 table of contents general description ......................................................................... 3 specifications ..................................................................................... 4 ad5384-5 specifications ............................................................. 4 ac characteristics ........................................................................ 6 ad5384-3 specifications ............................................................. 7 ac characteristics ........................................................................ 9 timing characteristics ................................................................... 10 serial interface ............................................................................ 10 i 2 c serial interface ...................................................................... 12 absolute maximum ratings .......................................................... 13 pin configuration and function descriptions ........................... 14 ter mi nolo g y .................................................................................... 17 typical performance characteristics ........................................... 18 functional description .................................................................. 21 dac architecturegeneral ..................................................... 21 data decoding ............................................................................ 21 on-chip special function registers (sfr) ............................ 22 sfr commands .......................................................................... 22 hardware functions ....................................................................... 25 reset function ............................................................................ 25 asynchronous clear function .................................................. 25 busy and ldac fu nctions ...................................................... 25 power-on reset .......................................................................... 25 power-down ............................................................................... 25 interfaces .......................................................................................... 26 dsp-, spi-, microwire-compatible serial interfaces ............ 26 i 2 c serial interface ..................................................................... 28 microprocessor interfacing ....................................................... 31 application information ................................................................ 32 power supply decoupling ......................................................... 32 monitor function ....................................................................... 32 toggle mode function ............................................................... 32 thermal monitor function ....................................................... 33 ad5384 in a mems-based optical switch ............................ 33 optical attenuators .................................................................... 34 outline dimensions ....................................................................... 35 ordering guide .......................................................................... 35 revision history 10/04changed from rev. 0 to rev. a changes to table 19........................................................................ 24 changes to ordering guide .......................................................... 35 7/04revision 0: initial version
ad5384 rev. a | page 3 of 36 general description the ad5384 is a complete single-supply, 40-channel, 14-bit dac available in a 100-lead cspbga package. all 40 channels have an on-chip output amplifier with rail-to-rail operation. the ad5384 includes an internal 1.25 v/2.5 v, 10 ppm/c reference, an on-chip channel monitor function that multiplexes the analog outputs to a common mon_out pin for external monitoring, and an output amplifier boost mode that allows the amplifier slew rate to be optimized. the ad5384 contains a serial interface compatible with spi, qspi, microwire, and dsp interface standards with interface speeds in excess of 30 mhz and an i 2 c-compatible interface supporting 400 khz data transfer rate. an input register followed by a dac register provides double buffering, allowing the dac outputs to be updated independently or simultaneously. using the ldac input. each channel has a programmable gain and offset adjust register letting the user fully calibrate any dac channel. power consumption is typically 0.25 ma/channel with boost mode off. table 1. complete family of high channel count, low voltage, single-supply dacs in portfolio model resolution av dd range output channels linearity error (lsb) package description package option ad5380bst-5 14 bits 4.5 v to 5.5 v 40 4 100-lead lqfp st-100 ad5380bst-3 14 bits 2.7 v to 3.6 v 40 4 100-lead lqfp st-100 ad5381bst-5 12 bits 4.5 v to 5.5 v 40 1 100-lead lqfp st-100 ad5381bst-3 12 bits 2.7 v to 3.6 v 40 1 100-lead lqfp st-100 ad5384bbc-5 14 bits 4.5 v to 5.5 v 40 4 100-lead cspbga bc-100 ad5384bbc-3 14 bits 2.7 v to 3.6 v 40 4 100-lead cspbga bc-100 ad5382bst-5 14 bits 4.5 v to 5.5 v 32 4 100-lead lqfp st-100 ad5382bst-3 14 bits 2.7 v to 3.6 v 32 4 100-lead lqfp st-100 ad5383bst-5 12 bits 4.5 v to 5.5 v 32 1 100-lead lqfp st-100 ad5383bst-3 12 bits 2.7 v to 3.6 v 32 1 100-lead lqfp st-100 ad5390bst-5 14 bits 4.5 v to 5.5 v 16 3 52-lead lqfp st-52 ad5390bcp-5 14 bits 4.5 v to 5.5 v 16 3 64-lead lfcsp cp-64 ad5390bst-3 14 bits 2.7 v to 3.6 v 16 4 52-lead lqfp st-52 ad5390bcp-3 14 bits 2.7 v to 3.6 v 16 4 64-lead lfcsp cp-64 ad5391bst-5 12 bits 4.5 v to 5.5 v 16 1 52-lead lqfp st-52 ad5391bcp-5 12 bits 4.5 v to 5.5 v 16 1 64-lead lfcsp cp-64 ad5391bst-3 12 bits 2.7 v to 3.6 v 16 1 52-lead lqfp st-52 ad5391bcp-3 12 bits 2.7 v to 3.6 v 16 1 64-lead lfcsp cp-64 ad5392bst-5 14 bits 4.5 v to 5.5 v 8 3 52-lead lqfp st-52 ad5392bcp-5 14 bits 4.5 v to 5.5 v 8 3 64-lead lfcsp cp-64 ad5392bst-3 14 bits 2.7 v to 3.6 v 8 4 52-lead lqfp st-52 ad5392bcp-3 14 bits 2.7 v to 3.6 v 8 4 64-lead lfcsp cp-64 table 2. 40-channel, bipolar voltage output dac model resolution analog supplies output channe ls linearity error (lsb) package package option ad5379abc 14 bits 11.4 v to 16.5 v 40 3 108-lead cspbga bc-108
ad5384 rev. a | page 4 of 36 specifications ad5384-5 specifications av dd = 4.5 v to 5.5 v; dv dd = 2.7 v to 5.5 v, agnd = dgnd = 0 v; external refin = 2.5 v; all specifications t min to t max , unless otherwise noted. table 3. parameter ad5384-5 1 unit test conditions/comments accuracy resolution 14 bits relative accuracy 2 (inl) 4 lsb max 1 lsb typical differential nonlinearity (dnl) C1/+2 lsb max gu aranteed monotonic by design over temperature zero-scale error 4 mv max offset error 4 mv max measured at code 32 in the linear region offset error tc 5 v/c typ gain error 0.024 % fsr max at 25c 0.06 % fsr max t min to t max gain temperature coefficient 3 2 ppm fsr/c typ dc crosstalk 3 0.5 lsb max reference input/output reference input 3 reference input voltage 2.5 v 1% for specified performance, av dd = 2 refin + 50 mv dc input impedance 1 m? min typically 100 m? input current 1 a max typically 30 na reference range 1 to v dd /2 v min/max reference output 4 enabled via cr10 in the ad5384 control register, cr12, selects the output voltage. output voltage 2.495/2.505 v min/max at ambient; cr12 = 1; optimized for 2.5 v operation 1.22/1.28 v min/max cr12 = 0 reference tc 10 ppm/c max temperature range: +25c to +85c 15 ppm/c max temperature range: ?40c to +85c output characteristics 3 output voltage range 2 0/av dd v min/max short-circuit current 40 ma max load current 1 ma max capacitive load stability r l = 200 pf max r l = 5 k? 1000 pf max dc output impedance 0.5 ? max monitor pin output impedance 500 ? typ three-state leakage current 100 na typ logic inputs (except sda/scl) 3 dv dd = 2.7 v to 5.5 v v ih , input high voltage 2 v min v il , input low voltage 0.8 v max input current 10 a max total for all pins. t a = t min to t max pin capacitance 10 pf max logic inputs (sda, scl only) v ih , input high voltage 0.7 dv dd v min smbus-compatible at dv dd < 3.6 v v il , input low voltage 0.3 dv dd v max smbus-compatible at dv dd < 3.6 v i in , input leakage current 1 a max v hyst , input hysteresis 0.05 dv dd v min c in , input capacitance 8 pf typ glitch rejection 50 ns max input filtering su ppresses noise spikes of less than 50 ns
ad5384 rev. a | page 5 of 36 parameter ad5384-5 1 unit test conditions/comments logic outputs ( busy , sdo) 3 v ol , output low voltage 0.4 v max dv dd = 5 v 10%, sinking 200 a v oh , output high voltage dv dd C 1 v min dv dd = 5 v 10%, sourcing 200 a v ol , output low voltage 0.4 v max dv dd = 2.7 v to 3.6 v, sinking 200 a v oh , output high voltage dv dd C 0.5 v min dv dd = 2.7 v to 3.6 v, sourcing 200 a high impedance leakage current 1 a max sdo only high impedance output capacitance 5 pf typ sdo only logic output (sda) 3 v ol , output low voltage 0.4 v max i sink = 3 ma 0.6 v max i sink = 6 ma three-state leakage current 1 a max three-state output capacitance 8 pf typ power requirements av dd 4.5/5.5 v min/max dv dd 2.7/5.5 v min/max power supply sensitivity 3 ?midscale/?v dd C85 db typ ai dd 0.375 ma/channel max outputs un loaded, boost off; 0.25 ma/channel typ 0.475 ma/channel max outputs unloaded, boost on; 0.32 5ma/channel typ di dd 1 ma max v ih = dv dd , v il = dgnd ai dd (power-down) 2 a max typically 200 na di dd (power-down) 20 a max typically 3 a power dissipation 80 mw max o utputs unloaded, boost off, av dd = dv dd = 5 v 1 ad5384-5 is calibrated using an external 2.5 v referenc e. temperature range for all versions: C40c to +85c. 2 accuracy guaranteed from v out = 10 mv to av dd C 50 mv. 3 guaranteed by characterization, not production tested. 4 default on the ad5384-5 is 2.5 v. programmable to 1.25 v via cr12 in the ad5384 control register; operating the ad5384-5 with a 1.25 v reference will lead to degraded accuracy specifications.
ad5384 rev. a | page 6 of 36 ac characteristics 1 av dd = 2.7 v to 3.6 v; dv dd = 2.7 v to 5.5 v, agnd = dgnd = 0 v. table 4. parameter ad5384-5 unit test conditions/comments dynamic performance output voltage settling time boost mode off, cr11 = 0 1/4 scale to 3/4 scale change settling to 1 lsb 8 s typ 10 s max slew rate 2 2 v/s typ boost mode off, cr11 = 0 3 v/s typ boost mode on, cr11 = 1 digital-to-analog glitch energy 12 nv-s typ glitch impulse peak amplitude 15 mv typ channel-to-channel isolation 100 db typ see the terminology section dac-to-dac crosstalk 1 nv-s typ see the terminology section digital crosstalk 0.8 nv-s typ digital feedthrough 0.1 nv-s typ effect of in put bus activity on dac output under test output noise 0.1 hz to 10 hz 15 v p-p typ ex ternal reference, midscale loaded to dac 40 v p-p typ internal reference, midscale loaded to dac output noise spectral density @ 1 khz 150 nv/hz typ @ 10 khz 100 nv/hz typ 1 guaranteed by design and characterization, not production tested. 2 the slew rate can be programmed via the current boost control bit (cr11) in the ad5384 control register.
ad5384 rev. a | page 7 of 36 ad5384-3 specifications av dd = 2.7 v to 3.6 v; dv dd = 2.7 v to 5.5 v, agnd = dgnd = 0 v; external refin = 1.25 v; all specifications t min to t max , unless otherwise noted. table 5. parameter ad5384-3 1 unit test conditions/comments accuracy resolution 14 bits relative accuracy 2 4 lsb max differential nonlinearity C1/+2 lsb max guaranteed monotonic over temperature zero-scale error 4 mv max offset error 4 mv max measured at code 64 in the linear region offset error tc 5 v/c typ gain error 0.024 % fsr max at 25c 0.1 % fsr max t min to t max gain temperature coefficient 3 2 ppm fsr/c typ dc crosstalk 3 0.5 lsb max reference input/output reference input 3 reference input voltage 1.25 v 1% for specified performance dc input impedance 1 m? min typically 100 m? input current 1 a max typically 30 na reference range 1 to av dd /2 v min/max reference output 4 output voltage 1.245/1.255 v min/max at ambient; cr12 = 0; optimized for 1.25 v operation 2.47/2.53 v min/max cr12 = 1 reference tc 10 ppm/c max temperature range: +25c to +85c 15 ppm/c max temperature range: ?40c to +85c output characteristics 3 output voltage range 2 0/av dd v min/max short-circuit current 40 ma max load current 1 ma max capacitive load stability r l = 200 pf max r l = 5 k? 1000 pf max dc output impedance 0.5 ? max monitor pin output impedance 500 ? typ three-state leakage current 100 na typ logic inputs (except sda/scl) 3 dv dd = 2.7 v to 3.6 v v ih , input high voltage 2 v min v il, input low voltage 0.8 v max input current 10 a max total for all pins; t a = t min to t max pin capacitance 10 pf max logic inputs (sda, scl only) v ih , input high voltage 0.7 dv dd v min smbus-compatible at dv dd < 3.6 v v il , input low voltage 0.3 dv dd v max smbus-compatible at dv dd < 3.6 v i in , input leakage current 1 a max v hyst , input hysteresis 0.05 dv dd v min c in , input capacitance 8 pf typ glitch rejection 50 ns max input filtering su ppresses noise spikes of less than 50 ns
ad5384 rev. a | page 8 of 36 parameter ad5384-3 1 unit test conditions/comments logic outputs ( busy , sdo) 3 v ol , output low voltage 0.4 v max sinking 200 a v oh , output high voltage dv dd C 0.5 v min sourcing 200 a high impedance leakage current 1 a max sdo only high impedance output capacitance 5 pf typ sdo only logic output (sda) 3 v ol , output low voltage 0.4 v max i sink = 3 ma 0.6 v max i sink = 6 ma three-state leakage current 1 a max three-state output capacitance 8 pf typ power requirements av dd 2.7/3.6 v min/max dv dd 2.7/3.6 v min/max power supply sensitivity 3 ?midscale/?v dd C85 db typ ai dd 0.375 ma/channel max outputs unload ed, boost off; 0.25 ma/channel typ 0.475 ma/channel max outputs unloaded, boost on; 0.325 ma/channel typ di dd 1 ma max v ih = dv dd , v il = dgnd ai dd (power-down) 2 a max typically 200 na di dd (power-down) 20 a max typically 1 a power dissipation 48 mw max o utputs unloaded, boost off, av dd = dv dd = 3 v 1 ad5384-3 is calibrated using an external 1.25 v re ference. temperature range is C40c to +85c. 2 accuracy guaranteed from v out = 10 mv to av dd C 50 mv. 3 guaranteed by characterization, not production tested. 4 default on the ad5384-3 is 1.25 v. programmable to 2.5 v via cr12 in the ad5384 control register; operating the ad5384-3 with a 2.5 v reference will lead to degraded accuracy specifications and limited input code range.
ad5384 rev. a | page 9 of 36 ac characteristics 1 av dd = 2.7 v to 3.6 v and 4.5 v to 5.5 v; dv dd = 2.7 v to 5.5 v; agnd = dgnd = 0 v. table 6. parameter ad5384-3 unit test conditions/comments dynamic performance output voltage settling time boost mode off, cr11 = 0 1/4 scale to 3/4 scale change settling to 1 lsb 8 s typ 10 s max slew rate 2 2 v/s typ boost mode off, cr11 = 0 3 v/s typ boost mode on, cr11 = 1 digital-to-analog glitch energy 12 nv-s typ glitch impulse peak amplitude 15 mv typ channel-to-channel isolation 100 db typ see the terminology section dac-to-dac crosstalk 1 nv-s typ see the terminology section digital crosstalk 0.8 nv-s typ digital feedthrough 0.1 nv-s typ effect of in put bus activity on dac output under test output noise 0.1 hz to 10 hz 15 v p-p typ ex ternal reference, midscale loaded to dac 40 v p-p typ internal reference, midscale loaded to dac output noise spectral density @ 1 khz 150 nv/hz typ @ 10 khz 100 nv/hz typ 1 guaranteed by design and characterization, not production tested. 2 the slew rate can be programmed via the current boost control bit (cr11 ) in the ad5384 control register.
ad5384 rev. a | page 10 of 36 timing characteristics serial interf a c e dv dd = 2.7 v t o 5.5 v ; a v dd = 4.5 v t o 5.5 v o r 2.7 v t o 3.6 v ; a g nd = d g nd = 0 v ; al l sp e c if ica t ion s t min to t max , u n l e ss ot he r w i s e no te d. t a bl e 7. p a r a me t e r 1 , 2 , 3 limit a t t min , t ma x u n i t d e s c r i p t i o n t 1 33 ns min sclk c y cle time t 2 13 ns min sclk high time t 3 13 ns min sclk lo w time t 4 13 ns min sy nc falling edge t o sclk falling edge setup time t 5 4 13 ns min 24 th sclk falling edge t o sy nc falling edge t 6 4 3 3 n s m i n m i nimum sy nc lo w ti me t 7 10 ns min m i nimum sy nc high time t 7a 50 ns min m i nimum sy nc high time in r e adbac k mode t 8 5 ns min da ta setup time t 9 4.5 ns min da ta hold time t 10 4 30 ns max 24th sclk falling edge t o busy falling edge t 11 670 ns max busy pulse wid t h lo w ( s ingle chan nel upd a te) t 12 4 2 0 n s m i n 24th sclk falling edge t o ld a c falling edge t 13 20 ns min ld a c pulse wid t h lo w t 14 100 ns max busy r i sing ed ge to d a c output r e spo n se time t 15 0 ns min busy rising edge t o ld a c falling edge t 16 100 ns min ld a c falling edge t o d a c outpu t r e sponse time t 17 8 s t y p d a c outpu t sett ling time boost mode off t 18 20 ns min clr pulse wid t h lo w t 19 1 2 s m a x clr pulse ac tiva tion time t 20 5 20 ns max sclk rising edge t o sd o v a lid t 21 5 5 n s m i n sclk falling edge t o sy nc ri s i n g e d g e t 22 5 8 ns min sy nc rising edge t o s c lk rising edge t 23 2 0 n s m i n sy nc rising edge t o ld a c falling edge 1 gua r a n t eed b y d e s i g n a n d ch a r a c t e ri za t i on , n o t pr oduc t i on t e st ed . 2 a l l i n put si g n a ls a r e sp eci f i e d wi t h t r = t f = 5 ns (10% t o 90 % of dv dd ), a n d a r e t i m e d fr om a v o lt a g e lev e l of 1.2 v . 3 see , f , an d . f i gur e 2 i gur e 3 f i gur e 5, f i gur e 6 4 st a n da lon e m o d e on ly . 5 dais y- cha i n mod e onl y . c l 50pf t o output pin v oh (min) or v ol (max) 200 a 200 a i ol i oh 04652-0-003 f i gure 2 . l o a d cir c ui t fo r di g i ta l o u tput t i m i ng
ad5384 rev. a | page 11 of 36 1 ldac active during busy 2 ldac active after busy busy sync ldac 1 ldac 2 clr v out v out 2 v out 1 din sclk 04652-0-004 t 7 t 8 t 9 t 4 t 3 t 1 t 2 t 5 t 17 t 17 t 12 t 13 t 18 t 19 t 16 t 14 t 10 t 15 t 13 t 11 t 6 db0 db23 24 24 12 f i g u re 3. s e r i a l in te r f ac e ti m i ng d i ag r a m (st a nd al one m o de) t 7a 24 48 sclk sync din sdo db23 db0 db23 db0 db23 db0 input word specifies register to be read undefined nop condition selected register data clocked out 03731-0-005 f i g u re 4. s e r i a l in te r f ac e ti m i ng d i ag r a m (d at a r e adb a c k m o de) t 7 t 8 t 9 t 20 t 4 t 3 t 1 t 2 t 22 t 21 t 13 t 23 24 48 sclk sync din sdo ldac db23 db0 db23 db0 db23 db0 input word for dac n undefined input word for dac n + 1 input word for dac n 04652-0-005 f i g u re 5. s e r i a l in te r f ac e ti m i ng d i ag r a m (d ais y - c ha in m o de)
ad5384 rev. a | page 12 of 36 i 2 c serial interf a c e dv dd = 2.7 v t o 5.5 v ; a v dd = 4.5 v t o 5.5 v o r 2.7 v t o 3.6 v ; a g nd = d g nd = 0 v ; al l sp e c if ica t ion s t min to t max , u n l e ss ot he r w i s e no te d. t a bl e 8. p a r a me t e r 1 limit a t t min , t ma x unit description f scl 400 kh z max scl clock fr e q uenc y t 1 2.5 s min scl c y cle time t 2 0.6 s min t high , scl high time t 3 1.3 s min t lo w , scl lo w time t 4 0.6 s min t hd ,st a , star t/r e pe a t ed star t c o ndition hold time t 5 100 ns min t su , d a t , da ta setup time t 6 2 0 . 9 s m a x t hd ,d a t , da ta hold time 0 s m i n t hd ,d a t , da ta hold time t 7 0.6 s min t su ,st a , setup tim e f o r r e pea t ed star t t 8 0.6 s m0in t su ,s t o , stop c o nd ition setup time t 9 1.3 s min t bu f , bus fr ee tim e bet w e e n a st op and a st ar t c o ndition t 10 300 ns max t r , rise time of scl and sd a wh en r e c e iving 0 ns min t r , r i se time of scl and sd a wh en r e c e i v ing ( c mos - c o mpa t ible) t 11 300 ns max t f , fall time of sd a when tr ansmitting 0 ns min t f , fall time of sd a when r e ceivin g ( c mos - c o mpatible) 300 ns max t f , fall time of scl and sd a when r e c e iving 20 + 0.1c b 3 ns min t f , fall time of scl and sd a when tr ansmitting c b 400 pf max c a paciti v e load f o r each bus li ne 1 see . f i gur e 6 2 a m a s t e r d e vi c e m u st pr o v i d e a h o l d t i m e of a t lea s t 300 n s f o r t h e sd a si g n a l ( r ef err e d t o t h e v ih m i n of t h e sc l si g n a l) i n o r de r t o b r i d ge t h e un d e fi n e d r e g i on of s c l s fa lli n g edge . 3 c b is the t o tal capacitance , in pf , of o n e bus l i ne . t r a n d t f are measured b e t w een 0.3 dv dd and 0. 7 dv dd . start condition repeated start condition stop condition t 9 t 3 t 1 t 11 t 4 t 10 t 4 t 5 t 7 t 6 t 8 t 2 sda scl 04652-0-006 fi g u r e 6 . i 2 c- c o m p a t i b le s e ri al int e r f ac e tim i ng d i a g r a m
ad5384 rev. a | page 13 of 36 absolute maximum ra tings t a = 2 5 c , u n l e ss ot he r w i s e no t e d. 1 t a bl e 9. p a r a me t e r r a ting av dd t o a g nd C0.3 v t o +7 v dv dd to dgnd C0.3 v to +7 v dig i tal i n puts to dgnd C0.3 v to d v dd + 0.3 v sd a/scl t o dg nd C0.3 v t o + 7 v dig i tal o utputs t o dgnd C0.3 v t o d v dd + 0.3 v refin/refout t o a g nd C0.3 v t o a v dd + 0.3 v a g nd t o dg nd C0.3 v t o +0.3 v vout x t o a g nd C0.3 v t o a v dd + 0.3 v analog i n puts t o a g nd C0.3 v t o a v dd + 0.3 v o p era t ing t e mp er a tur e r a nge c o mme r c ia l (b v e rsion) C40c to +85c stor age t e mpera tur e r a nge C65c to +150c j u nc tion t e mpera tur e ( t j max) 150c 100-lead cspbga p a ck age ja ther mal i m pedanc e 40c/w r e flo w s o ldering p e ak t e mpera tur e 230c 1 t r ansien t cur r en ts of up t o 100 m a do not cause scr la t c h-up . s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h os e list e d i n t h e op era t io nal s e c t ion s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . esd c a ution esd (elec t r o sta t i c dischar g e) sensitiv e devic e . ele c tr osta tic char g e s as high as 4000 v r e adily ac cumula t e on the human body and t e st eq uipmen t and can dis c har g e w i thout det e c t ion. al though this pr oduc t f e atur es pr oprietar y esd pr ot ec tion cir c uitr y , permanen t damage ma y oc cur on devic e s subjec ted to high ener gy elec tr o s ta tic dischar g e s . ther ef o r e , p r o p er esd pr ecaut i ons a r e r e c o m m ended to a v oid per f or m a nc e degrada t io n or los s of func tionalit y .
ad5384 rev. a | page 14 of 36 pin conf igura t ion and fu nction descriptions 04652-0-007 top view 123456789 1 0 1 1 1 2 123456789 1 0 1 1 1 2 a b c d e f g h j k l m a b c d e f g h j k l m f i g u re 7. 10 0-l e ad cspbg a p i n conf ig ur at i o n t a bl e 10. p i n n u mb er an d n a me cspbga number ball name cspbga number ball name cspbga number ball name c s p b g a number ball name c s p b g a number ball name a 1 n c b 9 rese t e 4 d a c g n d 4 h 1 1 v o u t 1 3 l 5 a g n d 5 a 2 v o u t 2 4 b 1 0 v o u t 2 2 e 9 d a c g n d 3 h 1 2 v o u t 1 4 l 6 v o u t 6 a3 clr b 1 1 n c e 1 1 v o u t 1 7 j 1 a v d d 1 l 7 v o u t 3 2 a4 sy nc b 1 2 v o u t 2 3 e 1 2 v o u t 1 9 j 2 v o u t 3 0 l 8 v o u t 3 4 a 5 s c l k c 1 v o u t 2 6 f 1 r e f g n d j 4 d a c g n d 5 l 9 v o u t 3 6 a 6 d v d d 1 c 2 signal gnd4 f 2 signal gnd1 j 5 a g n d 1 l 1 0 v o u t 3 8 a 7 d g n d c 1 1 n c f 4 d a c g n d 1 j 6 d a c g n d 2 l 1 1 n c a 8 p d c 1 2 v o u t 2 1 f 9 signal gnd3 j 7 d a c g n d 2 l 1 2 v o u t 9 a 9 d c e n d 1 v o u t 2 7 f 1 1 v o u t 1 6 j 8 a g n d 2 m 1 n c a10 ld a c d 2 signal gnd4 f 1 2 v o u t 1 8 j 9 signal gnd2 m 2 v o u t 3 a11 busy d 4 d a c g n d 4 g 1 v o u t 2 8 j 1 1 v o u t 1 2 m 3 v o u t 4 a 1 2 n c d 5 a g n d 4 g 2 v o u t 2 9 j 1 2 v o u t 1 1 m 4 v o u t 5 b 1 v o u t 2 5 d 6 d v d d 2 g 4 d a c g n d 1 k 1 v o u t 0 m 5 a v d d 5 b 2 n c d 7 d g n d g 9 s i g n a l g n d3 k 2 v o u t 1 m 6 v o u t 7 b 3 d g n d d 8 a g n d 3 g 1 1 v o u t 1 5 k 1 1 n c m 7 v o u t 3 3 b 4 d i n d 9 d a c g n d 3 g 1 2 a v d d 2 k 1 2 v o u t 1 0 m 8 v o u t 3 5 b 5 s d o d 1 1 v o u t 2 0 h 1 refout/refi n l 1 v o u t 2 m 9 v o u t 3 7 b 6 d v d d 3 d 1 2 a v d d 3 h 2 v o u t 3 1 l 2 n c m 1 0 v o u t 3 9 / mon_out b 7 d g n d e 1 a v d d 4 h 4 d a c g n d 5 l 3 signal gnd5 m 1 1 v o u t 8 b8 spi/ i 2 c e 2 signal gnd1 h 9 signal gnd2 l 4 signal gnd5 m 1 2 n c
ad5384 rev. a | page 15 of 36 t a bl e 11. p i n f u nc ti o n des c rip t i o ns mnemonic f u nc tion vout x buff er ed analog o utputs f o r channel x. each analog output is dr i v en b y a r a i l -to -rail output ampli f ier opera ting a t a gain of 2. each o utput is capable of dr iving an output load of 5 k? to gr ou nd . t y pical output impedanc e is 0.5 ? . signal g n d(1C 5) analog gr ound r e f e r e nc e p o in ts f o r each gr oup of eigh t o utput channels . all signal_gnd pins ar e tied t o gether in ter n ally and should be c o nne c ted to the a g nd plane as close as possible to the ad5384. d a c gnd ( 1C5) each gr oup of ei gh t channe ls co n t ains a d a c_gnd pin. this is the gr ound r e f e renc e poi n t f o r the in ter n al 14-b i t d a c. these pins shou nd be c o nnec t e d to the a g nd p l ane . a g nd(1C5 ) analog ground r e f e r e nc e p o i n t. each gr oup of e i gh t cha nne ls co n t ains a n a g nd pin. all a g nd pins should be c o nnec t ed ex ter n ally to the a g nd plane . a v dd(1C5 ) analog sup p ly p i ns . each gr ou p of eigh t chann e ls ha s a sep a ra te a v dd pin. the s e pins ar e s h or ted in ter n ally an d should be d e c o upled with a 0.1 f c e ramic ca p a citor an d a 10 f tan t alum capacit o r . o p er a t ing r a nge f o r the ad5384-5 is 4.5 v to 5.5 v ; oper a ting r a nge f o r the ad5384-3 is 2. 7 v to 3.6 v . dgnd gr ound f o r all dig i tal cir c uitr y . dvdd l o g i c p o w e r su pply . guar an tee d oper a ting r a nge is 2.7 v to 5.5 v . i t is r e c o mme nded th a t these pins be decoupled with 0.1 f c e r a mic and 10 f tan t alum capacitors to dgnd . ref gnd gr ound r e f e r e nc e p o in t f o r the i n ter n al r e f e r e nc e . refout/refin the ad5384 c o n t ains a c o mmon refout/refi n pin. the default f o r this pin is a r e f e r e nc e input. w h en the in ter n al r e f e r e nc e is sele c t ed , this pin is t h e r e f e r e nc e ou tput. i f the ap plica t ion r e quir es an ex ter n al r e f e r e nc e , it can be ap pli e d to this pin. the in ter n al r e f e r e nc e is e n a b led/disa bled vi a the c o n t r o l r e gister . vout39/mon_out this pin has a dual func tion. i t ac ts a a buff er ed o utput f o r channel 39 in default mode . but when the monit o r func tion is enabled , this pin ac ts as the output of a 39-to -1 chan nel multiple x e r tha t can be pr ogr a mmed to multiplex one of chann e ls 0 to 38 to the mon_out pin. the mo n_out pin output impeda n c e t y pically is 5 00 ? and is in tended to dr iv e a high input impedanc e li ke tha t exhi bited b y sar adc inputs . sy nc /ad0 s e r i al i n ter f ac e m o de . this is the fr ame synch r oniza t ion in put si gnal f o r the ser i al clo c ks bef o re the ad d r essed register is upda ted . i 2 c m o de . this pin ac ts as a h a r d w a r e addr es s pi n used in c o nju n c t ion with ad1 to d e ter mine th e sof t w a r e ad d r ess f o r the devic e on the i 2 c bus . dcen/ ad1 multifunc t ion p i n. i n ser i al in ter f ac e mode , this pin ac ts as a daisy- chain ena b le in spi mode and a s a har d w a r e addr es s pin in i 2 c mode . s e r i al i n ter f ac e . daisy- chai n sele c t input (lev el se nsitiv e , ac tiv e hi gh). when high, this si gna l is use d in c o njunc t ion with spi/ i 2 c high to enab le the spi ser i al in ter f ac e daisy- chain mo de . i 2 c m o de . this pin ac ts as a h a r d w a r e addr es s pi n used in c o nju n c t ion with ad0 to d e ter mine th e sof t w a r e ad d r ess f o r this devic e o n the i 2 c bus . sd o serial da ta o utput in s e r i al i n ter f ac e m o de . thr e e - sta t ea ble cm os output. sd o can be used f o r daisy- chaini ng a number of devic e s together . data is cloc ked out on sd o on th e rising edge of sclk , and is v a lid on the falling edge of sclk . dig i tal cmos o utput. busy g o e s l o w duri n g i n t e rn a l c a l c ula t ions of the da ta (x 2) loaded t o the d a c da ta r e g i st er . dur i ng this time , the user can c o n t inue wr iting new da ta to the x1, c , and m r e g i st ers , but no fur t her upda t e s t o the d a c r e g i st ers and d a c ou tputs can take plac e . i f ld a c is taken lo w w h ile busy is lo w , this ev e n t is stor e d . busy also goes low d u r i ng po w e r- on reset, and when the busy pin is low . dur i ng this time , the in ter f ac e is disabled and an y ev e n ts on ld a c ar e ig nor e d . a clr opera t i on al so br ings busy lo w . ld a c lo a d dac lo g i c i n p u t (ac t i v e low ) . i f ld a c is taken low while busy is inac tiv e (high), the c o n t en ts of the input r e gisters ar e tr a n sf er r e d to the d a c r e gisters , a n d the d a c outputs ar e upda te d . i f ld a c is taken low while busy is ac tiv e and in ter n al ca lcul a t ions ar e tak i ng pl ac e , the ld a c ev en t is sto r ed and the d a c r e gisters a r e upda ted when busy goes inac tiv e . ho w e v e r , an y ev en ts on ld a c dur i ng p o w e r - o n r e set o r on rese t ar e igno r e d . clr a s ynchr o nous clear i n put. t h e c l r in put is fallin g edge sensitiv e . w h en clr is ac tivated , all cha nnel s ar e upda ted with the da ta in the clr co d e r e gi s t e r . busy is lo w f o r a d u ra tion of 35 s while a ll ch anne ls are being upd a ted with the clr co d e . rese t a s ynchr o nous dig i tal r e set i n put (f alling edge s e nsitiv e). the func tion of this p i n is equivale n t to tha t of the pow er - on r e set gener a tor . w h en this pin is taken low , t h e sta t e ma ch in e initia tes a r e se t sequenc e to d i gitally r e set the x1, m, c , and x2 r e g i ste r s to their default po w e r - on v a lues . th is se quence t y pically take s 270 s . the falli ng edge of rese t initia tes the rese t pr o c ess a n d busy goes lo w f o r the dur a tion, r e turning high when rese t is c o m p lete . w h ile busy is low , all i n ter f a c es are d i sab l ed and all ld a c pulses a r e igno r e d . whe n busy r e tur ns high, the par t r e sume s nor m al opera tion and t h e sta tus of the rese t pin is ig nor e d un til the nex t falling edge is det e c t ed .
ad5384 rev. a | page 16 of 36 mnemonic function pd power down (level sensitive, active high). pd is used to place the device in low power mode, where ai dd reduces to 2 a and di dd to 20 a. in power-down mode, all internal analog circuitry is placed in low power mode, and the analog output is configured as a high impedance output or provides a 100 k? load to ground, depending on how the power-down mode is configured. the serial interface remains active during power-down. nc no connect. the user is advised not to connect any signals to these pins. spi/ i 2 c this pin acts as serial interface mode select. when th is input is high spi mode is selected. when low, i 2 c is selected. sclk/scl serial interface mode. in serial interface mode, data is clocke d into the shift register on the falling edge of sclk. this operates at clock speeds up to 30 mhz. i 2 c mode. in i 2 c mode, this pin performs the scl function, clocking data into the device. the data transfer rate in i 2 c mode is compatible with both 100 khz and 400 khz operating modes. din/sda serial interface mode. in serial interface mode, this pin acts as the serial data input. data must be valid on the falling edge of sclk. i 2 c mode. in i 2 c mode, this pin is the serial data pin (s da) operating as an open-drain input/output.
ad5384 rev. a | page 17 of 36 terminology relative accuracy relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero-scale error and full-scale error, and is expressed in lsb. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. zero-scale error zero-scale error is the error in the dac output voltage when all 0s are loaded into the dac register. ideally, with all 0s loaded to the dac and m = all 1s, c = 2 n C 1 vout ( zero-scale ) = 0 v zero-scale error is a measure of the difference between vout (actual) and vout (ideal), expressed in mv. it is mainly due to offsets in the output amplifier. offset error offset error is a measure of the difference between vout (actual) and vout (ideal) in the linear region of the transfer function, expressed in mv. offset error is measured on the ad5384-5 with code 32 loaded into the dac register, and on the ad5384-3 with code 64. gain error gain error is specified in the linear region of the output range between v out = 10 mv and v out = av dd C 50 mv. it is the deviation in slope of the dac transfer characteristic from the ideal and is expressed in %fsr with the dac output unloaded. dc crosstalk this is the dc change in the output level of one dac at midscale in response to a full-scale code (all 0s to all 1s, and vice versa) and output change of all other dacs. it is expressed in lsb. dc output impedance this is the effective output source resistance. it is dominated by package lead resistance. output voltage settling time this is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full-scale input change, and is measured from the busy rising edge. digital-to-analog glitch energy this is the amount of energy injected into the analog output at the major code transition. it is specified as the area of the glitch in nv-s. it is measured by toggling the dac register data between 0x1fff and 0x2000. dac-to-dac crosstalk dac-to-dac crosstalk is the glitch impulse that appears at the output of one dac due to both the digital change and the sub- sequent analog output change at another dac. the victim channel is loaded with midscale. dac-to-dac crosstalk is specified in nv-s. digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one converter due to a change in the dac register code of another converter. it is specified is specified in nv-s. digital feedthrough when the device is not selected, high frequency logic activity on the devices digital inputs can be capacitively coupled both across and through the device to show up as noise on the vout pins. it can also be coupled along the supply and ground lines. this noise is digital feedthrough. output noise spectral density this is a measure of internally generated random noise. random noise is characterized as a spectral density (voltage per hertz). it is measured by loading all dacs to midscale and measuring noise at the output. it is measured in nv/hz in a 1 hz band- width at 10 khz.
ad5384 rev. a | page 18 of 36 typical perf orm ance cha r acte ristics 03731-0-033 input code 16384 0 4096 8192 12288 inl e rror (ls b ) ?2.0 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 av dd = dv dd = 5.5v v ref = 2.5v t a = 25c f i gure 8. t y pic a l a d 5384-5 i n l p l ot 03731-0-034 sample number 550 0 100 150 200 250 300 50 350 400 500 450 amp l itude (v ) 2.523 2.539 2.538 2.537 2.536 2.535 2.534 2.533 2.532 2.531 2.530 2.529 2.528 2.527 2.526 2.525 2.524 av dd = dv dd = 5v v ref = 2.5v t a = 25c 14ns/sample number 1 lsb change around midscale glitch impulse = 10nv-s f i g u re 9. a d 53 84- 5 gli t ch i m pu ls e 03731-0-012 av dd = dv dd = 5v v ref = 2.5v t a = 25 c v out f i gure 1 0 . slew ra te wi th boo s t o ff 03731-0-035 input code 16384 0 4096 8192 12288 inl e rror (ls b ) ?2.0 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 av dd = dv dd = 3v v ref = 1.25v t a = 25c f i g u re 11. t y pic a l a d 53 8 4 -3 i n l p l ot 03731-0-048 reference drift (ppm/ c) ?5.0 ?1.5 2.5 ?3.5 ?4.5 ?4.0 0.5 ? 0.5 3.5 ?2.5 1.5 ?1.0 3.0 ? 3.0 1.0 0 4.0 5.0 4.5 ?2.0 2.0 fre q ue ncy 0 40 30 20 35 25 15 10 5 f i gure 12. a d 5 3 8 4 - r e f out t e mper at ur e coeffi ci ent 03731-0-015 av dd = dv dd = 5v v ref = 2.5v t a = 25 c v out f i gure 1 3 . slew ra te wi th boo s t o n
ad5384 rev. a | page 19 of 36 04598-0-049 ai dd (ma) 11 89 1 0 p e rce ntage of units (%) 14 12 10 8 6 4 2 av dd = 5.5v v ref = 2.5v t a = 25c f i g u re 14. h i s t og r a m w i t h b oos t o f f 04598-0-050 di dd (ma) 0.8 0.9 0.4 0.5 0.6 0.7 numbe r of units 0 10 8 6 4 2 dv dd = 5.5v v ih = dv dd v il = dgnd t a = 25c f i g u re 15. di dd his t og r a m 03731-0-045 av dd = dv dd = 5v v ref = 2.5v t a = 25 c exits soft pd to midscale v out busy wr f i g u re 16. e x it ing s o f t p o we r d o wn 03731-0-011 av dd = dv dd = 5v v ref = 2.5v t a = 25c power supply ramp rate = 10ms v out av dd f i gur e 1 7 . ad53 84 p o w e r - up t r a n sie n t 04652-0-039 inl error distribution (lsb) 2 ?2 ?1 0 1 num be r of uni ts 0 14 12 10 8 6 4 2 av dd = 5.5v refin = 2.5v t a = 25c f i gure 18. inl d i s t ri bution 03731-0-038 av dd = dv dd = 5v v ref = 2.5v t a = 25 c exits hardware pd to midscale pd v out f i gure 19. e x iting h a r d w a re p o w e r d o wn
ad5384 rev. a | page 20 of 36 04652-0-030 current (ma) ?40 ? 20 ? 1 0 ? 5 ? 2 0 2 5 10 20 40 v out (v ) ?1 6 4 3 2 5 1 0 zero-scale 1/4 scale midscale 3/4 scale full-scale av dd = dv dd = 5v v ref = 2.5v t a = 25c f i g u re 20. a d 5 3 8 4 - 5 o u t p ut a m p lif i e r s o u r c e and si nk ca pabi lit y 04652-0-040 i source /i sink (ma) 2.00 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 e rror v o ltage (v ) ? 0.20 0.20 0.10 0.05 0.15 0 ? 0.05 ? 0.10 ? 0.15 av dd = 5v v ref = 2.5v t a = 25 c error at zero sinking current (v dd ?v out ) at full-scale sourcing current f i g u re 21. h e ad r o o m at ra il v s . s o u r ce /sink cur r ent 04652-0-035 frequency (hz) 100k 100 1k 10k outp ut nois e (nv / hz) 0 600 500 400 300 200 100 av dd = 5v t a = 25c refout decoupled with 100nf capacitor refout = 2.5v refout = 1.25v f i g u re 22. r e fou t nois e spe c t r a l d e n s it y 04652-0-031 current (ma) ?40 ? 20 ? 1 0 ? 5 ? 2 0 2 5 10 20 ? 4 0 v out (v ) ?1 6 4 3 2 5 1 0 zero-scale 1/4 scale midscale 3/4 scale full-scale av dd = dv dd = 3v v ref = 1.25v t a = 25c f i g u re 23. a d 5 3 8 4 - 3 o u t p ut a m p lif i e r s o u r c e and si nk ca pabi lit y 04652-0-032 sample number 550 0 100 150 200 250 300 50 350 400 500 450 amp l itude (v ) 2.449 2.456 2.455 2.454 2.453 2.452 2.451 2.450 av dd = dv dd = 5v v ref = 2.5v t a = 25c 14ns/sample number f i gure 24. a d jac e nt chann e l d a c to da c cr osstalk av dd = dv dd = 5v v ref = 2.5v t a = 25c exits soft pd to midscale 04652-0-034 av dd = dv dd = 5v t a = 25c dac loaded with midscale external reference y axis = 5 v/div x axis = 100ms/div f i g u re 25. 0. 1 h z t o 10 h z no is e plot
ad5384 rev. a | page 21 of 36 functional description d a c architec ture g ener al the ad5384 is a complete sing le -supply, 40-channel, voltage output dac off e ring 14-bit res o lution, availabl e in a 100-lead cspbga pa ckage. it feat ures tw o seri a l i n t e rfaces, spi an d i 2 c. this family incl udes an in ternal 1.25/2.5 v, 10 p p m/c referen c e that can be used to d r ive the buffered referen c e inputs . alt e rna t ively , a n exter n al referen c e can be used to d r ive thes e inp u ts. r e ference sel e ctio n is v i a a bi t i n t h e control register. i n ter n a l /ext er nal r e fer e n c e s e le c t io n is v i a t h e cr10 b i t in t h e con t r o l r e g i s t er ; cr12 s e l e c t s t h e r e fer e nce ma g n i t ude if th e in t e r n al r e f e r e n c e is s e le c t e d . al l c h a n ne ls ha v e an o n -chi p o u t p u t a m p l if ier wi t h ra il-t o-rail o u t p u t ca p a b l e o f d r i v in g 5 k? in p a ral l e l wi th a 200 pf lo ad . 04652-0-014 v out r r 14-bit dac m reg c reg 1 input reg 2 input data v ref (+) avdd agnd f i gure 26. sing le - c hann el a r ch ite c t ure the architect u re of a sing le da c channel cons ists of a14-bit resistor-string dac followe d by an outpu t bu ffer amplif ier operati n g at a g a i n of 2. th is re sistor-stri n g arc h it ecture guara n tees da c monoto nici ty. the 14-bitbinary digital code loa d ed t o th e da c re gi st e r d e te rmi n es at w h ic h node on t h e string t h e voltage is t a pped off before bei n g fe d to the output ampl ifier. each ch a nnel o n th ese dev i ces co nta i ns in depe nde nt o ffset a n d gain con t rol registers allowin g th e user to digi ta lly trim offset and gain. these registers let the us er calibr ate o u t errors in the complete s i gn al chai n i n clu d i n g the d a c us ing the internal m and c registers whic h hol d the co rrection facto r s. all channels ar e do ubl e buff er ed allo wi ng sy nchr o n o u s up d a ti ng o f all channels using the ld a c pin. f i gur e 26 shows a block di agra m of a singl e channel on the ad5 384. the digital input transfer functio n fo r eac h da c ca n be r e pr esen ted as x2 = [( m + 2)/ 2 n x1 ] + ( c C 2 n C 1 ) w h er e: x2 i s th e d a ta -w o r d loa d ed t o t h e r e si s t o r s t ri n g d a c . x1 is t h e 14- b i t da t a -w o r d wr i t ten t o t h e d a c i n p u t r e g i st er . m is t h e ga in co ef f i cien t (defa u l t is 0x3ffe o n th e ad5384). the ga i n co ef f i cien t is wr i t ten to t h e 13 m o st si g n if ica n t b i ts (d b13 t o d b 1) a nd t h e ls b (db0) is 0. n i s th e d a c r e so l u ti o n ( n = 14 f o r ad5384). c is t h e14-b i t o f f s et co ef f i cien t (defa u l t is 0x2000). the complet e tr ansfer fu nctio n for these devic e s can b e r e p r es en t e d as v ou t = 2 v ref x2 /2 n w h er e: x2 i s th e d a ta -w o r d loa d ed t o t h e r e si s t o r s t ri n g d a c . v ref is t h e i n t e r n al r e fer e n c e v o l t a g e o r t h e r e fer e n c e v o l t a g e e x te r n a l ly a p plied t o t h e d a c refo ut/ref in p i n. f o r s p eci f ie d pe rf o r manc e, an e x te r n a l re fe re nc e vo l t age of 2 . 5 v i s r e co mm ended fo r th e ad5384-5, a nd 1.25 v f o r th e ad5384-3 . d a t a dec o ding the ad5384 co ntains a 14-bit data bus , db13-db0. depending on th e value of reg1 and reg0 outlin ed in t a b l e 12, this data is lo ad ed in to the a ddr e sse d d a c input register(s), offset (c) register(s), or gain (m) register (s). t h e fo rmat data, offset (c) and gai n (m) re gis t er co nt e n ts are outl i n e d in t a b l e 13, t a b l e 1 4 , and t a b l e 15. t a bl e 12. r e g i st e r s e l e c t i o n reg1 reg0 regist er s e lec t ed 1 1 i n put da ta r e g i ster (x1) 1 0 o f f s et r e g i ster (c) 0 1 g a in r e g i ster (m) 0 0 special f u nc tio n r e gisters ( s frs) t a bl e 13. d a c da ta f o rma t (reg1 1, reg 0 1) db13 t o db0 d a c o u tput ( v ) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 v ref (16383/16384) 1 1 1 1 1 1 1 1 1 1 1 1 1 0 2 v ref (16382/16384) 1 0 0 0 0 0 0 0 0 0 0 0 0 1 2 v ref (8193/16384) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2 v ref (8192/16384) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 v ref (8191/16384) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 v ref (1/16384) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 t a bl e 14. o f f s e t da ta f o rma t (reg1 1, reg 0 0) db13 t o db0 o f f s et (lsb) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + 8 1 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 + 8 1 9 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 + 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 C 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 C 8 1 9 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C 8 1 9 2
ad5384 rev. a | page 22 of 36 table 15. gain data format (reg1 = 0, reg0 = 1) db13 to db0 gain factor 11 1111 1111 1110 1 10 1111 1111 1110 0.75 01 1111 1111 1110 0.5 00 1111 1111 1110 0.25 00 0000 0000 0000 0 on-chip special function registers (sfr) the ad5384 contains a number of special function registers (sfrs), as outlined in table 16. sfrs are addressed with reg1 = reg0 = 0 and are decoded using address bits a5 to a0. table 16. sfr register functions (reg1 = 0, reg0 = 0) r/ w a5 a4 a3 a2 a1 a0 function x 0 0 0 0 0 0 nop (no operation) 0 0 0 0 0 0 1 write clr code 0 0 0 0 0 1 0 soft clr 0 0 0 1 0 0 0 soft power-down 0 0 0 1 0 0 1 soft power-up 0 0 0 1 1 0 0 control register write 1 0 0 1 1 0 0 control register read 0 0 0 1 0 1 0 monitor channel 0 0 0 1 1 1 1 soft reset sfr commands nop (no operation) reg1 = reg0 = 0, a5Ca0 = 000000 performs no operation but is useful in serial readback mode to clock out data on d out for diagnostic purposes. busy pulses low during a nop operation. write clr code reg1 = reg0 = 0, a5Ca0 = 000001 db13Cdb0 = contain the clr data bringing the clr line low or exercising the soft clear function loads the contents of the dac registers with the data contained in the user-configurable clr register, and sets vout0 to vout39, accordingly. this can be very useful for setting up a specific output voltage in a clear condition. it is also beneficial for calibration purposes; the user can load full scale or zero scale to the clear code register and then issue a hardware or software clear to load this code to all dacs, removing the need for individual writes to each dac. default on power-up is all 0s. soft clr reg1 = reg0 = 0, a5Ca0 = 000010 db13Cdb0 = dont care executing this instruction performs the clr, which is functionally the same as that provided by the external clr pin. the dac outputs are loaded with the data in the clr code register. it takes 35 s to fully execute the soft clr, as indicated by the busy low time. soft power-down reg1 = reg0 = 0, a5Ca0 = 001000 db13Cdb0 = dont care executing this instruction performs a global power-down that puts all channels into a low power mode that reduces the analog supply current to 2 a maximum and the digital current to 20 a maximum. in power-down mode, the output amplifier can be configured as a high impedance output or can provide a 100 k? load to ground. the contents of all internal registers are retained in power-down mode. no register can be written to while in power-down. soft power-up reg1 = reg0 = 0, a5Ca0 = 001001 db13Cdb0 = dont care this instruction is used to power up the output amplifiers and the internal reference. the time to exit power-down is 8 s. the hardware power-down and software function are internally combined in a digital or function. soft reset reg1 = reg0 = 0, a5Ca0 = 001111 db13Cdb0 = dont care this instruction is used to implement a software reset. all internal registers are reset to their default values, which correspond to m at full scale and c at zero. the contents of the dac registers are cleared, setting all analog outputs to 0 v. the soft reset activation time is 135 s.
ad5384 rev. a | page 23 of 36 table 17. control register contents msb lsb cr13 cr12 cr11 cr10 cr9 cr8 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 control register write/read reg1 = reg0 = 0, a5Ca0 = 001100, r/ w status determines if the operation is a write (r/ w = 0) or a read (r/ w = 1). db13 to db0 contain the control register data. control register contents cr13: power-down status. this bit is used to configure the output amplifier state in power-down. cr13 = 1: amplifier output is high impedance (default on power-up). cr13 = 0: amplifier output is 100 k? to ground. cr12: ref select. this bit selects the operating internal reference for the ad5384. cr12 is programmed as follows: cr12 = 1: internal reference is 2.5 v (ad5384-5 default), the recommended operating reference for ad5384-5. cr12 = 0: internal reference is 1.25 v (ad5384-3 default), the recommended operating reference for ad5384-3. cr11: current boost control. this bit is used to boost the current in the output amplifier, thereby altering its slew rate. this bit is configured as follows: cr11 = 1: boost mode on. this maximizes the bias current in the output amplifier, optimizing its slew rate but increasing the power dissipation. cr11 = 0: boost mode off (default on power-up). this reduces the bias current in the output amplifier and reduces the overall power consumption. cr10: internal/external reference. this bit determines if the dac uses its internal reference or an externally applied reference. cr10 = 1: internal reference enabled. the reference output depends on data loaded to cr12. cr10 = 0: external reference selected (default on power-up). cr9: channel monitor enable (see channel monitor function). cr9 = 1: monitor enabled. this enables the channel monitor function. after a write to the monitor channel in the sfr register, the selected channel output is routed to the mon_out pin. vout39 operates as the mon_out pin. cr9 = 0: monitor disabled (default on power-up). when the monitor is disabled, the mon_out pin assumes its normal dac output function. cr8: thermal monitor function. this function is used to monitor the ad5384 internal die temperature, when enabled. the thermal monitor powers down the output amplifiers when the temperature exceeds 130c. this function can be used to protect the device when power dissipation might be exceeded if a number of output channels are simultaneously short-circuited. a soft power-up re-enables the output amplifiers if the die temperature drops below 130c. cr8 = 1: thermal monitor enabled. cr8 = 0: thermal monitor disabled (default on power-up). cr7: dont care. cr6 to cr2: toggle function enable. this function allows the user to toggle the output between two codes loaded to the a and b register for each dac. control register bits cr6 to cr2 are used to enable individual groups of eight channels for operation in toggle mode. a logic 1 written to any bit enables a group of channels; a logic 0 disables a group. ldac is used to toggle between the two registers. table 18 shows the decoding for toggle mode operation. for example, cr6 controls group w, which contains channels 32 to 39, cr6 = 1 enables these channels. cr1 and cr0: dont care. table 18. cr bit group channels cr6 4 32C39 cr5 3 24C31 cr4 2 16C23 cr3 1 8C15 cr2 0 0C7 channel monitor function reg1 = reg0 = 0, a5Ca0 = 001010 db13Cdb8 = contain data to address the monitored channel. a channel monitor function is provided on the ad5384. this feature, which consists of a multiplexer addressed via the interface, allows any channel output to be routed to the mon_out pin for monitoring using an external adc. in channel monitor mode, vout39 becomes the mon_out pin, to which all monitored pins are routed. the channel monitor function must be enabled in the control register before any channels are routed to mon_out. on the ad5384, db13 to db8 contain the channel address for the monitored channel. selecting channel address 63 three-states mon_out.
ad5384 rev. a | page 24 of 36 t a bl e 19. a d 53 84 c h anne l m o nit o r de co din g r e g 1 r e g 0 a 5 a 4 a 3 a 2 a 1 a 0 db 1 3 d b 1 2 d b 1 1 d b 1 0 d b 9 d b 8 d b 7 C d b 0 m o n _ o u t 0 0 0 0 1 0 1 0 0 0 0 0 0 0 x v o u t 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 x v o u t 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 x v o u t 2 0 0 0 0 1 0 1 0 0 0 0 0 1 1 x v o u t 3 0 0 0 0 1 0 1 0 0 0 0 1 0 0 x v o u t 4 0 0 0 0 1 0 1 0 0 0 0 1 0 1 x v o u t 5 0 0 0 0 1 0 1 0 0 0 0 1 1 0 x v o u t 6 0 0 0 0 1 0 1 0 0 0 0 1 1 1 x v o u t 7 0 0 0 0 1 0 1 0 0 0 1 0 0 0 x v o u t 8 0 0 0 0 1 0 1 0 0 0 1 0 0 1 x v o u t 9 0 0 0 0 1 0 1 0 0 0 1 0 1 0 x v o u t 1 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 x v o u t 1 1 0 0 0 0 1 0 1 0 0 0 1 1 0 0 x v o u t 1 2 0 0 0 0 1 0 1 0 0 0 1 1 0 1 x v o u t 1 3 0 0 0 0 1 0 1 0 0 0 1 1 1 0 x v o u t 1 4 0 0 0 0 1 0 1 0 0 0 1 1 1 1 x v o u t 1 5 0 0 0 0 1 0 1 0 0 1 0 0 0 0 x v o u t 1 6 0 0 0 0 1 0 1 0 0 1 0 0 0 1 x v o u t 1 7 0 0 0 0 1 0 1 0 0 1 0 0 1 0 x v o u t 1 8 0 0 0 0 1 0 1 0 0 1 0 0 1 1 x v o u t 1 9 0 0 0 0 1 0 1 0 0 1 0 1 0 0 x v o u t 2 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 x v o u t 2 1 0 0 0 0 1 0 1 0 0 1 0 1 1 0 x v o u t 2 2 0 0 0 0 1 0 1 0 0 1 0 1 1 1 x v o u t 2 3 0 0 0 0 1 0 1 0 0 1 1 0 0 0 x v o u t 2 4 0 0 0 0 1 0 1 0 0 1 1 0 0 1 x v o u t 2 5 0 0 0 0 1 0 1 0 0 1 1 0 1 0 x v o u t 2 6 0 0 0 0 1 0 1 0 0 1 1 0 1 1 x v o u t 2 7 0 0 0 0 1 0 1 0 0 1 1 1 0 0 x v o u t 2 8 0 0 0 0 1 0 1 0 0 1 1 1 0 1 x v o u t 2 9 0 0 0 0 1 0 1 0 0 1 1 1 1 0 x v o u t 3 0 0 0 0 0 1 0 1 0 0 1 1 1 1 1 x v o u t 3 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 x v o u t 3 2 0 0 0 0 1 0 1 0 1 0 0 0 0 1 x v o u t 3 3 0 0 0 0 1 0 1 0 1 0 0 0 1 0 x v o u t 3 4 0 0 0 0 1 0 1 0 1 0 0 0 1 1 x v o u t 3 5 0 0 0 0 1 0 1 0 1 0 0 1 0 0 x v o u t 3 6 0 0 0 0 1 0 1 0 1 0 1 1 0 1 x v o u t 3 7 0 0 0 0 1 0 1 0 1 0 0 1 1 0 x v o u t 3 8 0 0 0 0 1 0 1 0 1 0 0 1 1 1 x v o u t 3 9 0 0 0 0 1 0 1 0 1 0 1 0 0 0 x u n d e f i n e d ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 1 0 1 0 1 1 1 1 1 0 x u n d e f i n e d 0 0 0 0 1 0 1 0 1 1 1 1 1 1 x thr e e - sta t e 04652-0-015 db13? db8 channel address ad5384 channel monitor decoding 0 000 101 0 vout0 vout1 vout37 vout38 vout39/mon_out reg1 reg0 a5 a4 a3 a2 a1 a0 f i gure 27. channe l monitor d ecoding
ad5384 rev. a | page 25 of 36 hardware functions reset function bringing the reset line low resets the contents of all internal registers to their power-on reset state. reset is a negative edge- sensitive input. the default corresponds to m at full scale and to c at zero. the contents of the dac registers are cleared, setting vout0 to vout39 to 0 v. the hardware reset activation time takes 270 s. the falling edge of reset initiates the reset process; busy goes low for the duration, returning high when reset is complete. while busy is low, all interfaces are disabled and all ldac pulses are ignored. when busy returns high, the part resumes normal operation and the status of the reset pin is ignored until the next falling edge is detected. asynchronous clear function bringing the clr line low clears the contents of the dac registers to the data contained in the user configurable clr register and sets vout0 to vout39 accordingly. this function can be used in system calibration to load zero scale and full scale to all channels. the execution time for a clr is 35 s. busy and ldac functions busy is a digital cmos output that indicates the status of the ad5384. the value of x2, the inte rnal data loaded to the dac data register, is calculated each time the user writes new data to the corresponding x1, c ,or m registers. during the calculation of x2, the busy output goes low. while busy is low, the user can continue writing new data to the x1, m, or c registers, but no dac output updates can take place. the dac outputs are updated by taking the ldac input low. if ldac goes low while busy is active, the ldac event is stored and the dac outputs update immediately after busy goes high. the user can hold the ldac input permanently low, in which case the dac outputs update immediately after busy goes high. busy also goes low during power-on reset and when a falling edge is detected on the reset pin. during this time, all interfaces are disabled and any events on ldac are ignored. the ad5384 contains an extra feature whereby a dac register is not updated unless its x2 register has been written to since the last time ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the contents of the x2 registers. however, the ad5384 updates the dac register only if the x2 data has changed, thereby removing unnecessary digital crosstalk. power-on reset the ad5384 contains a power-on reset generator and state machine. the power-on reset resets all registers to a predefined state and configures the analog outputs as high impedance. the busy pin goes low during the power-on reset sequencing, preventing data writes to the device. power-down the ad5384 contains a global power-down feature that puts all channels into a low power mode and reduces the analog power consumption to 2 a maximum and digital power consumption to 20 a maximum. in power-down mode, the output amplifier can be configured as a high impedance output or it can provide a 100 k? load to ground. the contents of all internal registers are retained in power-down mode. when exiting power-down, the settling time of the amplifier elapses before the outputs settles to their correct values.
ad5384 rev. a | page 26 of 36 interfaces the ad5384 contains a serial interface that can be programmed either as dsp-, spi-, microwire-, or i 2 c- compatible. the spi/ i2c pin is used to select dsp, spi, microwire, or i 2 c interface mode. to minimize both the power consumption of the device and the on-chip digital noise, the active interface powers up fully only when the device is being written to, i.e., on the falling edge of sync . dsp-, spi-, microwire-compatible serial interfaces the serial interface can be operated with a minimum of three wires in standalone mode or five wires in daisy-chain mode. daisy chaining allows many devices to be cascaded together to increase system channel count. the spi/ i2c (ball b8) should be tied high to enable the dsp- , spi-, microwire-compatible serial interface. the serial interface control pins are sync , din, sclk standard 3-wire interface pins. dcen selects standalone mode or daisy-chain mode. sdo data out pin for daisy-chain mode. figure 3 and figure 5 show the timing diagrams for a serial write to the ad5384 in standalone and in daisy-chain modes. the 24-bit data-word format for th e serial interface is shown in table 20. a /b . when toggle mode is enabled, this selects whether the data write is to the a or b register, with toggle disabled this bit should be set to zero to select the a data register. r/ w is the read or write control bit. a5Ca0 are used to address the input channels. reg1 and reg0 select the register to which data is written, as shown in table 12. db13Cdb0 contain the input data-word. x is a dont care condition. standalone mode by connecting dcen (daisy-chain enable) pin low, standalone mode is enabled. the serial interface works with both a continuous and a noncontinuous serial clock. the first falling edge of sync starts the write cycle and resets a counter that counts the number of serial clocks to ensure that the correct number of bits are shifted into the serial shift register. any further edges on sync , except for a falling edge, are ignored until 24 bits are clocked in. once 24 bits are shifted in, the sclk is ignored. for another seri al transfer to take place, the counter must be reset by the falling edge of sync . table 20. 40-channel, 14-bit dac serial input register configuration msb lsb a /b r/ w a5 a4 a3 a2 a1 a0 reg1 reg0 db13 db12 db 11 db10 db9 db8 db7 db6 db 5 db4 db3 db2 db1 db0
ad5384 rev. a | page 27 of 36 dai s y - c h ai n m o d e f o r sy stem s t h a t co n t ain s e ver a l de vices, t h e sd o p i n can b e us e d to da isy - cha i n s e ver a l de v i ces to get h er . t h is da isy - chai n m o de can be us ef u l in sys t em dia g n o s t ics an d in r e d u cin g t h e n u m b e r o f se ri al i n t e rfa c e l i n e s. by co nnect ing dcen ( d ai sy -c hai n e n a b le) pi n h i gh, t h e da is y - chai n mo de is e n a b led . t h e fir s t falli ng e d ge o f sy n c starts the write cy cle. th e sclk is appli e d cont inuously to the i n put s h if t register when sy n c is low. if more than 24 clock pu lses are applied, the data ripples out of the s h ift reg i ste r and appe ars on the sd o li ne. t h is dat a is clo c k e d o u t o n t h e r i sing e d ge o f sclk an d is v a l i d o n the f a lli ng edge. by co n n e c ting the s d o of the first dev i ce to the din i n put on t h e nex t dev i ce i n t h e chai n, a mul t i d e v ice i n t e rface is constructe d. 24 clock pulses are required for each d e vice in th e s y stem. therefore, the total number of clock cycles mus t e q ual 24n w h ere n is t h e tot a l number of ad5 384 devices in the chain. when t h e s e rial transfer to all devices is comple te, sy n c is tak e n hig h . thi s latch e s t h e i n p u t da ta in e a ch dev i ce i n t h e da isy - ch ai n a n d pr event s a n y fur t her d a ta be ing clo c ked i n to the i n put s h if t register. if t h e sy n c is tak e n hig h bef o r e 24 c l o c ks a r e c l o c k e d in t o t h e p a r t , t h is is co n s ider e d a b a d f r a m e and t h e d a t a is dis c a r de d . the seri al clock may be eit h er a conti n uous or a gat e d clock. a continuous scl k source can be us ed only if it c a n b e arra nge d tha t sy n c is hel d low for the correct number of clock cycles. in gate d clo c k mo de a bur s t clo c k co ntai n i ng t h e ex act nu mb er o f clock cycles mu st be used and sy n c take n h i gh after the fi na l clock to latc h th e da ta. re a d b a c k m o d e re a d b a ck m o de is in v o k e d b y s e t t in g t h e r/ w bit = 1 i n t h e se ri al i n p u t r e gis t e r w r i t e . w i th r / w = 1, bi ts a5 to a0, in as s o c i a t io n wi th b i ts reg1 and reg0, s e le c t t h e r e g i s t er t o be r e ad . the r e ma i n in g da t a b i ts i n t h e wr i t e s e q u e n ce a r e do n t ca r e s. d u r i n g t h e n e xt sp i wr i t e, t h e da t a a p p e ar in g o n t h e sd o o u t p ut co n t ain s t h e da t a f r o m t h e p r e v io u s l y addr es s e d r e g i st e r . f o r a r e ad o f a sin g le r e g i st er , t h e n o p co mmand can b e us e d in clo c k i n g o u t t h e da t a f r o m t h e s e le c t e d r e g i st er o n s d o . fi g u r e 2 8 s h ow s t h e r e a d b a c k s e q u e n c e . f o r exa m ple , t o r e ad b a ck t h e m r e g i s t er o f c h a nne l 0 o n t h e ad5384, t h e f o l l o w in g s e q u en c e sh o u ld be f o l l o w ed . f i rs t, wr i t e 0x404x x x t o t h e ad5384 in p u t r e g i s t er . this co nf igur es th e ad5384 f o r r e ad m o de wi t h t h e m r e g i s t er o f cha nne l 0 s e lec t e d . n o t e t h a t d a ta bi ts db13 t o d b 0 a r e do n t c a r e s. f o l l o w this wi th a s e con d wr i t e , a n o p con d i t ion, 0x000000. d u r i ng t h i s w r ite, t h e d a t a f r om t h e m re g i ste r i s cl o c ke d out on t h e s d o li ne, i . e., da t a clo c k e d o u t co n t ain s t h e d a t a f r o m t h e m r e g i s t er in bi ts d b 13 t o d b 0, a nd t h e t o p 10 b i ts co n t ain t h e addr ess info r m a t io n as p r e v io usly wr i tten . i n r e ad b a ck m o de, th e sy n c sig n al m u st f r a m e t h e da ta . d a t a is c l o c k e d o u t o n th e r i sin g edg e o f sclk an d is valid o n t h e f a l l i n g edge o f the sclk sig n a l . i f t h e s c lk id les hig h b e twe e n t h e wr i t e and r e ad op e r a t i o ns of a re a d b a c k op e r a t i o n , t h e f i r s t bit of d a t a i s cl o c ke d out o n t h e f a l l i n g e d ge of sy n c . 04652-0-016 24 48 sclk sync din sdo undefined selected register data clocked out nop condition input word specifies register to be read db23 db0 db0 db23 db0 db23 f i g u re 28. s e ri al r e adba ck o p er at i o n
ad5384 rev. a | page 28 of 36 i 2 c serial interface the ad5384 features an i 2 c-compatible 2-wire interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl facilitate communication between the ad5384 and the master at rates up to 400 khz. figure 6 shows the 2-wire interface timing diagrams that incorporate three different modes of operation. select i 2 c mode by configuring the spi/ i2c pin to a logic 0. the device is connected to this bus as slave devices, i.e., no clock is generated by the ad5384. the ad5384 has a 7-bit slave address 1010 1(ad1)(ad0). the 5 msbs are hard coded, and the two lsbs are determined by the state of the ad1 ad0 pins. the ability to hardware-configure ad1 and ad0 allows four of these devices to be configured on the bus. i 2 c data transfer one data bit is transferred during each scl clock cycle. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high are control signals, which configure start and stop conditions. both sda and scl are pulled high by the external pull-up resistors when the i 2 c bus is not busy. start and stop conditions a master device initiates communication by issuing a start condition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to-high transition on sda while scl is high. a start condition from the master signals the beginning of a transmission to the ad5384. the stop condition frees the bus. if a repeated start condition (sr) is generated instead of a stop condition, the bus remains active. repeated start conditions a repeated start (sr) condition may indicate a change of data direction on the bus. sr may be used when the bus master is writing to several i 2 c devices and wants to maintain control of the bus. acknowledge bit (ack) the acknowledge bit (ack) is the ninth bit attached to any 8-bit data-word. ack is always generated by the receiving device. the ad5384 devices generate an ack when receiving an address or data by pulling sda low during the ninth clock period. monitoring ack allows detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault occurs. in the event of an unsuccessful data transfer, the bus master should re-attempt communication. slave addresses a bus master initiates communication with a slave device by issuing a start condition followed by the 7-bit slave address. when idle, the ad5384 waits for a start condition followed by its slave address. the lsb of the address word is the read/write (r/ w ) bit. the ad5384 devices are receive-only devices; when communicating with these, r/ w = 0. after receiving the proper address 1010 1(ad1)(ad0), the ad5384 issues an ack by pulling sda low for one clock cycle. the ad5384 has four different user programmable addresses determined by the ad1 and ad0 bits. write operation there are three specific modes in which data can be written to the ad5384 family of dacs. 4-byte mode when writing to the ad5384 dacs, the user must begin with an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. the address byte is followed by the pointer byte; this addresses the specific channel in the dac to be addressed and also is acknowledged by the dac. two bytes of data are then written to the dac, as shown in figure 29. a stop condition follows. this lets the user update a single channel within the ad5384 at any time and requires four bytes of data to be transferred from the master. 3-byte mode in 3-byte mode, the user can update more than one channel in a write sequence without having to write the device address byte each time. the device address byte is required only once; sub- sequent channel updates require the pointer byte and the data bytes. in 3-byte mode, the user begins with an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. the address byte is followed by the pointer byte. this addresses the specific channel in the dac to be addressed and also is acknowledged by the dac. this is then followed by the two data bytes, reg1 and reg0, which determine the register to be updated. if a stop condition does not follow the data bytes, another channel can be updated by sending a new pointer byte followed by the data bytes. this mode requires only three bytes to be sent to update any channel once the device is initially addressed, and reduces the software overhead in updating the ad5384 channels. a stop condition at any time exits this mode. figure 30 shows a typical configuration.
ad5384 rev. a | page 29 of 36 1 0 1 0 1 ad1 ad0 r/w 0 0 a5 a4 a3 a2 a1 a0 scl sd a scl sd a start cond by master ack by ad538x ack by ad538x address byte most significant byte least significant byte pointer byte msb ack by ad538x ack by ad538x stop cond by master reg1 reg0 msb lsb msb lsb 04652-0-017 f i g u re 29. 4-b y t e a d 53 8 4 , i 2 c w r ite o p er at ion 04652-0-018 scl s d a s d a scl s d a scl s d a scl start cond by master ack by ad538x msb address byte pointer byte for channel "n" most significant data byte pointer byte for channel "next channel" least significant data byte most significant data byte least significant data byte ack by ad538x ack by ad538x data for channel "n" data for channel "next channel" ack by ad538x 1 0 0 a5 a4 a3 a2 a1 a0 0 1 0 0 0 a5 a4 a3 a2 a1 a0 1 ad1 ad0 r / w r e g 1 r e g 0 msb l s b msb l s b msb ack by ad538x ack by ad538x ack by ad538x stop cond by master reg1 reg0 msb lsb msb lsb f i g u re 30. 3-b y t e a d 53 8 4 , i 2 c w r ite o p er at ion
ad5384 rev. a | page 30 of 36 2-b y t e m o d e fo l l ow i n g i n it i a l i z a t i o n o f 2 - by t e m o d e , t h e u s e r c a n up d a t e cha nnels s e q u e n t i a l ly . t h e de v i ce ad dr ess b y te is r e q u ir e d o n ly o n ce, and t h e p o in ter a ddr ess p o in ter is co nf ig ur e d fo r a u to - i n cr em en t o r b u r s t m o d e . the us er m u st b e g i n w i t h a n a d dr ess b y te (r/ w = 0), a f t e r which t h e d a c ac kno w le dg es t h a t i t is p r ep a r ed t o r e cei v e da t a b y p u l l in g sd a lo w . the ad dr ess b y t e is fol l o w e d b y a sp e c if ic p o in t e r b y te (0xff) t h a t in i t ia t e s t h e b u rst m o d e o f o p era t io n . the ad dr ess p o i n t e r in i t ia l i zes to c h a nnel 0,and , u p on r e ceivi n g th e t w o da ta b y t e s f o r th e p r e s en t a d d r e s s, a u t o m a ti call y i n cr em en t s t o t h e n e xt ad d r e s s. the reg0 and reg1 b i ts i n t h e da t a b y te de t e r m ine w h ich r e g i st er is u p d a te d . i n t h is m o d e , fol l o w in g t h e ini t i a li za t i on, o n ly t h e tw o da t a b y tes a r e r e q u i r e d to u p da te a cha nnel. t h e cha nnel a ddr ess a u to ma t i c a l l y in cr e m en ts f r o m a ddr ess 0. this m o de a l lo w s t r a n smissio n o f da t a to a l l cha n nels in on e b l o c k a nd r e d u ces t h e s o f t wa r e o v er he ad i n co nf igur i n g a l l cha n nels. a sto p con d i t ion a t an y t i me ex i t s t h is mo de. t o g g l e m o de is n o t s u p p o r t e d in 2-b y t e m o de . f i gur e 31 sh o w s a typ i cal co nf igura t io n. 1 0 1 0 1 ad1 ad0 r/w 0 0 a5 = 1 a4 = 1 a3 = 1 a2 = 1 a1 = 1 a0 = 1 start cond by master address byte pointer byte most significant data byte channel 0 data least significant data byte ack by ad538x msb ack by ad538x ack by ad538x ack by ad538x most significant data byte channel 1 data least significant data byte ack by ad538x ack by converter most significant data byte channel n data followed by stop least significant data byte ack by ad538x ack by converter stop cond by master reg1 reg0 msb lsb msb lsb reg1 reg0 msb lsb msb lsb reg1 reg0 msb lsb msb lsb scl sda scl sda scl sda scl sda 04652- 0- 019 f i g u re 31. 2-b y t e , 1 2 c w r ite o p er ati o n
ad5384 rev. a | page 31 of 36 micr oprocessor interf a c ing a d 53 84 to mc 68 hc 11 the s e r i al p e r i ph eral i n ter f ace ( s p i ) o n t h e mc 68h c11 is co nf igur e d fo r mas t er m o de (ms t r = 1), t h e c l o c k p o la r i ty b i t (cpo l) = 0, a nd t h e c l o c k p h as e b i t (cph a) = 1. the s p i is co nf igur e d b y w r i t in g t o t h e s p i co n t r o l r e g i st er (s pcr)s e e th e 68 h c 11 u s er m a n u al . sck o f th e 68h c11 dr i v es t h e scl k o f th e ad5384, th e m o s i ou t p u t dr i v es t h e s e r i al da t a lin e (d in ) o f th e ad5384, a nd t h e miso in p u t is dr i v en f r o m d ou t . the sy n c sig n a l is de r i ve d f r o m a p o r t lin e (pc7). w h e n da t a is bein g tra n smi t t e d t o t h e ad5 384, th e s y nc l i ne is tak e n lo w ( p c 7 ) . d a t a a p p e ar i n g on t h e m o si output i s v a l i d on t h e fal l in g e d g e o f s c k. s e r i al da ta f r o m th e 68h c11 is tra n smi t t e d in 8- b i t b y t e s w i t h o n ly eig h t f a l l in g clo c k e d ges o c c u r r i n g i n th e tra n sm i t c y c l e . 04652-0-020 mc68hc11 ad5384 miso mosi sck pc7 sdo reset spi/i 2 c din sclk sync dvdd f i gur e 3 2 . ad53 84 -t o m c68h c11 inte r f a c e a d 53 84 to p i c 1 6 c 6x/ 7 x t h e pic 1 6 c 6 x / 7 x s y nch r onou s s e r i a l p o r t ( s sp ) i s c o n f i g u r e d as a n s p i mas t er wi t h t h e c l o c k p o la r i ty b i t = 0. this is don e b y w r i t i n g t o t h e syn c h r o n o u s se r i al po r t c o n t r o l r e gi s t e r (ss p co n). s e e th e p i c16/17 micr o c o n tr ol ler u s er m a n u al . i n this exa m p l e i/o , p o r t ra1 is bein g us ed t o p u ls e sy n c a nd ena b le t h e s e r i al p o r t o f th e ad5384. this micro c o n tr ol ler tra n sf e r s o n l y e i gh t b i t s o f da ta d u ri n g e a c h se rial tra n sf e r o p era t ion; t h er e f o r e , t h r e e co n s e c u t i v e r e ad/ w r i t e o p era t io n s co u l d b e ne e d e d , de p e n d in g on t h e m o de. f i g u r e 33 sh o w s t h e co nn ec t i o n dia g ra m. 04652-0-021 pic16c6x/7x ad5384 sdi/rc4 sdo/rc5 sck/rc3 ra1 sdo reset spi/i 2 c din sclk sync dvdd f i g u re 33. a d 5 3 8 4 - t o - pic 1 6c6x / 7 x in t e r f ace a d 53 84 to 8 0 5 1 the ad5384 r e q u ir es a c l o c k syn c hr o n ize d t o th e s e r i al da ta . the 8051 s e r i al in t e r f ace m u s t t h er ef o r e be op era t ed in m o de 0 . i n t h i s mo de, s e r i a l da t a e n ters a nd ex i t s t h r o u g h rx d , an d a s h if t c l o c k is o u t p u t on txd . f i gur e 34 s h o w s ho w t h e 8051 is co nn ec t e d t o t h e ad5384. b e ca us e the ad5384 s h if ts da t a o u t o n t h e r i sin g e d g e o f t h e s h if t cl o c k an d la t c h e s da t a in on t h e fal l in g e d g e , t h e s h if t c l o c k m u st be in v e r t ed . th e ad5384 r e q u ir es i t s da ta t o be ms b f i rst. s i nce t h e 8051 o u t p u t s t h e ls b f i r s t , t h e tra n smi t r o u t in e m u s t tak e th i s i n t o a c co un t . 04652-0-022 8xc51 ad5384 rxd txd p1.1 sdo reset spi/i 2 c din sclk sync dvdd dvdd f i gur e 3 4 . ad53 84 -t o - 805 1 int e r f a c e a d 53 84 to a d s p -21 01/ a d s p -21 0 3 f i gur e 35 sh o w s a s e r i al in t e r f ac e betw e e n t h e ad5384 a nd t h e ads p -2101/ads p -2103. the ad s p -2101 /ads p - 2103 sh o u ld b e s e t up to op e r a t e i n sp o r t t r ans m it a l te r n at e f r am i n g mo d e . the ads p -210 1/ads p -2103 s p o r t is p r og ra mm e d thr o ug h t h e sp or t c o n t ro l re g i ste r and shou l d b e c o n f i g u r e d a s f o l l o w s : in t e r n a l clo c k op era t ion, ac t i ve lo w f r a m in g , and 16-b i t w o r d len g t h . t r a n smi s sio n is in i t ia t e d b y wr i t ing a w o r d t o t h e tx r e g i s t er a f t e r t h e s p o r t has b e en ena b le d . 04652-0-023 adsp-2101/ adsp-2103 ad5384 dr dt sck tfs rfs sdo reset spi/i 2 c din sclk dvdd sync f i gur e 3 5 . ad53 84 -t o - adsp -210 1/ adsp -2 10 3 int e r f a c e
ad5384 rev. a | page 32 of 36 appli c a t ion inf o rma t ion po wer suppl y dec o upling i n an y cir c ui t w h er e acc u rac y is im p o r t a n t, c a r e f u l co n s idera - t i on of t h e p o w e r supply an d g r ou n d re tu r n l a y o ut h e lp s to en s u r e t h e ra t e d p e r f o r ma n c e . th e p r i n t e d cir c u i t b o a r d o n which t h e ad5 384 is m o u n t e d s h o u l d be desig n e d s o tha t t h e a n a l o g a nd d i g i t a l s e c t io n s a r e s e p a r a te d and conf in e d to cer t a i n a r eas o f th e bo a r d . i f t h e ad5384 is in a sys t em w h er e m u l t i p le de vice s r e q u ir e a n a g nd- t o-d g nd co nn e c t i o n , t h e c o n n e c t i on s h o u l d b e m a d e a t one p o i n t on ly , a st ar g r ou n d p o in t est a b l ish e d as clos e t o t h e de vice as p o ssib le . f o r s u p p lies wi t h m u l t i p le p i n s (a v dd , a v cc ), t h es e p i n s sh o u ld be tied t o g e t h er . the ad5384 sh o u ld ha v e am ple s u p p l y b y p a s s - in g o f 10 f in p a ral l e l wi th 0 . 1 f o n eac h s u p p l y , lo ca t e d as cl o s e to t h e p a ck age a s p o ss ibl e an d i d e a l l y r i g h t up ag ai nst t h e de vic e . th e 10 f ca p a ci t o rs a r e t h e t a n t al u m b e ad typ e . the 0.1 f ca p a ci t o r s h o u l d ha ve lo w ef f e c t i v e s e r i es r e sis t a n ce (es r ) a nd ef f e c t i v e ser i es in d u c t a n c e (es i ), lik e th e co mm o n cera mic ty p e s t h a t p r o v id e a lo w im p e dan c e p a t h t o g r o u n d a t hig h f r e q ue n c ie s, t o ha ndle t r a n sien t c u r r en ts d u e t o in t e r n al log i c swi t ching. the p o wer s u p p l y lin e s o f t h e ad5384 sh o u ld u s e as la rg e a t r ace as p o s s ib le t o p r o v ide lo w im p e dan c e p a t h s a nd r e d u ce t h e ef fe c t s o f g l i t c h e s o n t h e p o w e r su p p l y line . f a s t swi t c h in g sig n als, s u c h as c l o c ks, sh o u l d b e s h ie lde d wi t h dig i tal g r o u n d to a v oi d r a d i a t i n g noi s e to ot he r p a r t s of t h e b o ard, an d s h ou l d ne ver b e r u n ne a r t h e r e fer e n c e in p u ts. a g r o u nd li n e r o u t e d bet w een t h e d in a nd scl k lin e s he l p s t o r e d u ce cr os s t al k bet w een t h em (th i s i s n o t r e q u ir ed o n a m u l t i l a y e r boa r d b e c a us e t h er e is a s e p a ra te g r o u nd plan e , b u t s e p a ra t i n g t h e lin e s he l p s). i t is es s e n t i a l t o mi nimi ze n o is e o n t h e v in and refin lin e s. a v o i d cr o s s o ver o f dig i t a l an d ana l o g sig n a l s. t r aces o n o p p o si t e sides o f th e bo a r d sh ou ld r u n a t r i g h t a n g l es t o e a ch ot he r . t h i s re d u c e s t h e e f f e c t s of f e e d t h rou g h t h rou g h t h e bo a r d . a micr os tr i p t e c h niq u e is b y fa r t h e bes t , b u t is n o t a l wa ys p o ss i b le wi t h a doub le-si d e d b o a r d . i n t h is t e chni q u e , t h e co m p on e n t side o f t h e b o a r d is de dic a te d to t h e g r o u n d pla n e w h i l e sig n al t r aces a r e place d o n t h e s o lde r side . monit o r func tio n the ad5384 con t a i n s a c h ann e l m o ni t o r f u n c tio n tha t co n s is ts o f a m u l t i p lexer addr ess e d v i a t h e in t e r f ace, a l l o w i n g an y ch annel out p ut to b e route d to t h i s pi n for mon i tor i ng u s i n g a n ex ter n a l ad c. i n cha n nel m o ni to r m o de, v o u t 39 b e com e s t h e mon _ ou t pi n, to w h i c h a l l mon i tore d s i g n a l s are route d . the cha n nel mo ni to r f u n c t i o n m u st b e enab le d i n t h e co n t r o l re g i ste r b e f o re a n y ch an n e l s are route d to m o n _ ou t . c o n t ai ns t h e de co di n g in fo r m a t io n r e q u i r e d to r o u t e an y cha nnel to mo n_o u t . s e le c t in g c h a n ne l a ddr es s 63 t h r e e-s t a t es m o n _ ou t . fi g u re 3 6 show s a t y pi c a l mo n i tor i ng c i rc u i t im ple m e n t e d usin g a 12 -b i t sa r ad c in a 6-le ad sot p a ck a g e. the co n t r o l l er o u t p ut p o r t s e le c t s t h e cha n ne l to b e m o ni t o r e d , a nd t h e in p u t p o r t r e ads t h e con v er t e d da t a f r o m t h e a d c. ad7476 gnd sdata cs sclk avcc v in vout39/mon_out agnd din sync sclk dac_gnd signal_gnd vout0 vout38 avcc ad5384 output port input port controller 04652-0-024 f i gure 36. t y pic a l c h ann e l m o n i to ri ng circuit t o ggle mode fu nc tion t h e t o ggl e m o de fu n c ti o n all o ws a n o u t p u t s i gnal t o be g e n e r- at e d u s i n g t h e ld a c co n t r o l sig n al , w h ic h s w i t ch es b e tw een tw o d a c da t a r e g i st ers. this f u n c t i on is co nf ig ur e d usin g t h e s f r co n t r o l r e g i s t er as fol l o w s. a wr i t e w i t h reg1 = reg0 = 0 a nd a5Ca0 = 001100 s p ecif ies a co n t r o l r e g i s t er wr i t e . th e t o ggl e m o d e fun c ti o n i s e n a b l e d in gr o u p s o f e i gh t c h a n n e l s usin g b i ts cr6 to cr2 in t h e con t r o l r e g i s t er (s ee t a b l e 17). fi g u r e 3 7 s h ow s a b l o c k d i a g r a m o f t o g g l e m o d e i m p l em en ta ti o n . 14-bit dac dac register input data input register data register b data register a a/b v out ldac control input 04652-0-025 f i g u re 37. t o gg l e m o de f u nc t i on
ad5384 rev. a | page 33 of 36 e a c h o f the 40 d a c c h a n ne ls o n t h e ad5384 co n t a i n s a n a and b da t a r e g i s t er . n o t e t h a t t h e b r e g i s t ers can b e lo ade d o n l y w h en t o g g l e mo de is ena b le d . th e s e q u e n ce o f e v en ts w h e n co nf igur in g t h e ad5384 f o r t o g g l e mo de is 1. ena b le t o g g l e mo de fo r t h e r e q u ir e d cha n ne ls v i a t h e c o n t ro l re g i ste r . 2. loa d d a ta t o a r e gi s t e r s . 3. loa d d a ta t o b r e gi s t e r s . 4. ap p l y ld a c . the ld a c is us ed t o swi t c h betw e e n t h e a an d b r e g i s t ers in deter m ini n g t h e a n a l o g o u t p ut. the f i rst ld a c co nf igur es t h e o u t p ut t o r e f l e c t t h e da t a i n t h e a r e g i s t ers. thi s m o de o f fers sig n if ican t a d van t a g es if t h e us e r wa n t s t o ge n e r a t e a s q ua r e wa v e a t t h e o u t p u t o f al l 40 c h anne ls, as mig h t be r e q u ir ed t o dr i v e a l i q u id cr ys tal-bas e d va r i a b le o p tical a t t e n u a t o r . i n this cas e , t h e us er w r i t es t o t h e con t r o l r e g i s t er a n d ena b les t h e t o g g l e f u n c t i o n b y s e t t in g cr6 to cr2 = 1, th us ena b lin g t h e f i v e g r o u ps o f eig h t fo r t o g g l e mo de o p er a t io n. the us er m u s t th en l o a d da ta t o all 4 0 a a n d b r e gi s t e r s . t o ggli n g ld a c se t s t h e ou t p u t va l u es t o r e f l e c t t h e da t a in t h e a and b r e g i s t ers. the f r e q uen c y o f t h e ld a c det e r m i n es t h e f r e q ue n c y o f t h e sq u a r e w a v e o u t p u t . t o g g l e m o de is dis a b l e d v i a t h e co n t r o l r e g i s t er . the f i rs t ld a c fol l o w in g t h e di s a b l ing o f t h e to g g l e mo de up da tes t h e o u t p u t s w i t h th e d a ta c o n t a i n e d i n th e a r e gi s t e r s . thermal m o nit o r fu nc tio n the ad5384 con t a i n s a t e m p er a t ur e s h u t do wn f u n c tion t o p r o t e c t t h e c h i p if m u l t i p le ou t p u t s a r e sh o r t e d . the sh o r t- cir c ui t c u r r en t o f e a ch o u t p u t am plif ier is ty p i c a l l y 40 ma. o p era t in g t h e ad5384 a t 5 v leads t o a p o w e r dis s i p a t io n o f 200 mw p e r sho r t e d a m p l if ier . w i t h f i v e c h a n ne ls sh o r t e d , this le ads to a n ex t r a wa t t o f p o w e r dissi p a t io n. f o r t h e 100 -le a d cs p b g a , t h e ja is typ i c a l l y 44c/w . the t h er mal mo ni t o r is ena b le d b y t h e us er v i a cr8 in t h e co n t r o l r e g i s t er . the o u t p u t am p l if iers o n t h e ad5384 a r e a u t o ma t i c a l l y p o w e r e d do w n if t h e di e t e m p era t ur e exce e d s a p p r o x ima t e l y 130c. af t e r a t h er mal s h u t do wn has o c c u r r ed , t h e us er ca n r e - e na b l e t h e p a r t b y exe c u t in g a s o f t p o w e r - u p if t h e te m p e r atu r e d r op s b e l o w 1 3 0 c , or b y tu r n i n g of f t h e t h er ma l m o ni t o r f u n c t i o n v i a t h e con t r o l r e g i s t er . ad5384 in a mems -b ased optic a l swit ch i n t h ei r f eed - f o r w a r d co n t r o l pa th s , mems ba se d o p tical s w itc h e s re qu i r e h i g h re s o lut i on d a c s t h a t of f e r h i g h ch an n e l den s i t y wi t h 14-b i t m o n o t o nic b e ha vio r . th e 40 -c ha nn el , 14-b i t ad5384 d a c s a tisf ies th es e r e q u ir em en ts. i n t h e c i r c ui t in f i gur e 38, t h e 0 v t o 5 v o u t p u t s o f th e ad5384 a r e a m p l if ied t o ac hieve a n o u t p u t ra n g e o f 0 v t o 200 v , w h ic h is us ed t o co n t r o l a c t u a t o r s th a t d e t e rmin e th e posi ti o n o f mems m i rr o r s i n a n opt i c a l s w itch . t h e e x a c t p o s i t i on of e a c h m i r r or i s me a s u r e d u s i n g s e ns or s . t h e s e ns or output s ar e m u lt ipl e x e d i n t o a h i g h r e so l u ti o n ad c in de t e rm in i n g th e m i rr o r posi ti o n . the co n t r o l lo op is c l os ed a nd dr i v en b y a n ads p -21065l, a 3 2 - bit sh a r c ? d s p w i t h an sp i - c o m p a t ibl e sp o r t i n te r f a c e. the ad s p -210 65l wr i t es da t a t o t h e d a c, con t r o ls t h e m u l t i - plexer , a n d r e ads da t a f r o m t h e ad c v i a t h e s e r i al in t e r f ace . actuators for mems mirror array sensor and multiplexer 8-channel adc (ad7856) or single-channel adc (ad7671) ad5384 14-bit dac 14-bit dac refout refina avdd vout1 vout40 g = 50 g = 50 output range 0v ? 200v adsp-21065l 0.01 f 04652-0-026 5v f i gur e 3 8 . ad53 84 in a mems-ba s e d o p ti c a l s w i t c h
ad5384 rev. a | page 34 of 36 o p t i c a l at t e n u at o r s b a s e d o n i t s hi g h cha n nel co un t , hig h r e s o l u t i on, m o n o to nic b e ha vio r , and hig h leve l o f in t e g r a t io n, t h e ad5 384 is ideal l y t a rget e d a t o p t i c a l a t t e n u a t io n a p plica t io n s us e d i n d y namic g a i n e q u a l i z e r s , v a r i a b l e opt i c a l a tte n u ator s ( v o a ) , an d opt i c a l add-dr o p m u l t i p lex e r s (o ad ms). i n t h es e a p p l ica t io n s , each wa velen g t h is i ndivi d u a l ly ex t r ac te d usin g an a r r a ye d w a ve guide; i t s p o w e r is m o n i t o r e d usin g a ph o t o d i o d e , t r a n sim p e d - anc e a m pl i f i e r , an d an a d c i n a cl o s e d - l o o p c o n t rol s y ste m . the ad5384 con t r o ls th e o p t i c a l a t t e n u a t o r f o r eac h wa ve len g t h , ensur i n g tha t t h e p o w e r is e q ua lize d in al l w a v e le n g t h s be f o r e be i n g m u l t i p le x e d o n t o t h e f i be r . t h i s p r e v en ts info r m a t io n loss and s a t u r a t i o n f r o m o c c u r r in g a t a m plif ic a t ion st a g es f u r t h e r a l on g t h e f i b e r . attenuator attenuator attenuator attenuator awg awg fibre fibre dwdm out optical switch 11 12 1n? 1 1n dwdm in ad5384, 40-channel, 14-bit dac n:1 multiplexer 16-bit adc controller tia/log amp (ad8304/ad8305) adg731 (40:1 mux) ad7671 (0-5v, 1msps) photodiodes add ports drop ports 04652-0-027 f i g u re 39. oa dm u s ing t h e a d 53 8 4 as p a r t of an o p t i c a l at tenuat or
ad5384 rev. a | page 35 of 36 outline dimensions b c d e f g h j k l m a seating plane 0.34 nom 0.29 min detaila 0.50* 0.45 0.40 ball diameter 0.12 max coplanarity 0.80 bsc 8.80 bsc 12 11 1 0 9 8 7 654 32 1 a1 corner index area top view bottom view 10.00 bsc sq ball a1 pad corner detail a 2.50 sq 1.40 1.35 1.20 1.11 1.01 0.91 0.65 ref *compliant to jedec standards mo-205ac with the exception of ball diameter. f i gur e 4 0 . 10 0 - le ad chi p sc al e pa c k age bal l gri d ar ra y [csp _bga] (bc-10 0- 2) dimens ions sh ow n in millimet ers ordering guide m o d e l r e s o l u t i o n t e mper a t ur e r a n g e av dd ra n g e ou t p u t channels linearit y err o r (lsb) p a ck age description p a ck age op t i o n ad5384bbc-5 14 bits C40c to +85c 4.5 v to 5.5 v 40 4 100-l e ad cspb ga bc-100-2 AD5384BBC-5REEL7 14 bits C40c t o +85c 4.5 v t o 5.5 v 40 4 100-l e ad cspb ga bc-100-2 ad5384bbc-3 14 bits C40c to +85c 2.7 v to 3.6 v 40 4 100-l e ad cspb ga bc-100-2 ad5384bbc-3reel7 14 bits C40c t o +85c 2.7 v t o 3.6 v 40 4 100-l e ad cspb ga bc-100-2
ad5384 rev. a | page 36 of 36 notes p u r c h a se o f li c e n s e d i 2 c c o m p on en t s o f an a l og devi c e s or on e of i t s subli c en s e d a s s oci a t e d c o m p a n i e s c o n v ey s a li c e n s e f o r t h e pur c h a ser un der t h e p h i li p s i 2 c p a te nt r i ghts t o us e the s e co mpo n e n ts in an i 2 c sy st em , pr o v i d e d t h a t t h e sy st em c o n f orm s t o t h e i 2 c stand a rd sp ecif ica t ion as d e f i ned b y p h il ips. ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d04652C0C 10/04(a)

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